The present invention relates to a synchronizing circuit for detecting sync signals contained in a digital input signal and for properly protecting the synchronization when the sync signals drop out.
Digital audio systems have been recently developed because an audio reproduction of high quality can be achieved. The digital audio systems are grouped into a system which uses a magnetic tape and a system which uses a disc. As one example of the latter system, a compact disc (CD) system in which digital data recorded on a compact disc are optically read out by a laser beam has been developed and put into practical use.
In the case of the compact disc, as is well known, digital data are subjected to an EF (eight-bit to fourteen-bit) modulation arranged in one frame in a given format to be recorded on a disc. One frame of digital data includes a frame sync signal disposed at the head of the frame, a plurality of audio data words, and error correcting bits and consists of 588 channel bits in total. The sync signal consists of 24 channel bits and has a specific variation pattern sufficient to be distinguished from any other digital data.
In audio reproduction the frame sync signals are used for generating control signals for dividing frames and dividing digital data in one frame at a given unit. To this end, the playback apparatus is provided with a sync signal detecting circuit. A sync protecting circuit is further used in combination with the sync signal detecting circuit for interpolating sync signals when the sync signals drop out due to scratches on a disc.
FIG. 1 shows a prior sync circuit containing the sync signal detecting circuit and the sync protecting circuit, and FIGS. 2A and 2B are timing diagrams for explaining the operation of the sync circuit of FIG. 1.
In FIG. 1, a digital input signal applied to an input terminal 1 and having N bits per frame is applied to a sync signal detecting circuit 3, together with a clock signal generated on the basis of an output signal of a PLL circuit for detecting clock components contained in the digital signal reproduced from a disc, thereby to detect a frame sync signal for each frame. The output of sync signal detecting circuit 3 is connected to a gate circuit 4. The output of gate circuit 4 is connected to a clear terminal of a 1/N frequency divider (scale-of-N counter) for frequency-dividing the clock signal. The output of 1/N frequency divider 5 is connected to a window generator 6 of which the output is connected to a counter 7 which is cleared by an output signal of gate circuit 4. A selector 8 couples the output of window generator 6 or the counter 7 to a control terminal of gate circuit 4. The output of 1/N frequency divider 5 is connected to an output terminal 9.
In the sync circuit thus constructed, sync signal detecting circuit 3 detects the sync signal contained in each frame of the input signal and outputs a detect signal to gate circuit 4. Gate circuit 4 controls the supply of the sync detect signal from sync signal detecting circuit 3 to 1/N frequency divider 5 according to an output signal of selector 8. Frequency divider 5 is cleared every time an output signal of gate circuit 4 becomes high to provide a frame sync control signal to output terminal 9 for every N bits of the clock signal. Window generator 6 increases its output during a period of several bits in and near the N-th bit at which the next frame sync control signal is to be produced starting from a bit at which a frame sync control signal is produced by frequency divider 5, that is to say, generates a window to make gate circuit 4 conductive through selector 8. When sync signal detecting circuit 3 is well synchronized with frequency divider 5, selector 8 applies a window output of window generator 6 to gate circuit 4 to apply an output signal of sync signal detecting circuit 3 to frequency divider 5, through a window corresponding to the sync signal of the preceding frame. Owing to this operation, an erroneous operation due to noise other than true sync detect signals can be prevented.
If the frame sync signals cannot be detected due to dropout or the like, output signals of sync signal detector circuit 3 and gate circuit 4 cannot be obtained as shown in FIG. 2A. Even in this case, output signals appear every N bits at output terminal 9 through the frequency dividing operation of frequency divider 5, as shown in FIG. 2A. This indicates that the sync signals are interpolated. When the sync signals are not detected, counter 7 is not cleared and counts up the output of gate 4 for every frame by the window outputs of window generator 6. When counter 7 reaches a preset count, e.g. four frames, its output becomes high. In response, selector 8 enables gate circuit 4. Under this condition, a first output signal of sync detector circuit 3 passes through gate circuit 4 to clear frequency divider 5 and counter 7. When frequency divider 5 is cleared, an output signal appears at output terminal 9.
However, as shown in FIG. 2B, if a first output signal of sync signal detector circuit 3 is noise after the output of counter 7 has gone high, then the noise output clears frequency divider 5 and counter 7. Therefore, window generator 6 produces window outputs which are dependent on the noise output. Accordingly, notwithstanding, the sync signals are correctly detected after the noise output, since the window outputs of window generator 6 and the sync detect output signals of sync signal detector circuit 3 are not timed, no output signal is produced by gate circuit 4. After frequency divider 5 has been cleared by the noise output erroneous sync control signals are produced every N bits at output terminal 9 through the frequency dividing operation. Frequency divider 5 and sync signal detector 3 are synchronized with each other when the output of counter 7 goes high and a correct sync signal is detected.
As described above, the prior art sync circuit has a disadvantage in that, when some sync signals drop out due to some cause, erroneous sync control signals may be formed by the influence of noise so that the synchronizing operation of a digital signal processing circuit is lost.